Increased repairability of a memory array typically means more hardware, such as redundancy circuits, fuses and register elements, is required. This increase in hardware components also means an increase in chip size to accommodate these components. However, in the early design phase, especially when a new memory design and/or technology is still in its development stage, increased repairability of a memory array leads to not only the higher yield of the memory chip, but also an environment for debugging for future design or technology improvement.
Today's high-density memories, especially dynamic random access memory (DRAM) macro, embedded or not, comprise many sub-arrays called banks. Each bank comprises numerous smaller memory units called blocks or micro-cells. FIGS. 1A–B show prior art row redundancy storage 10 and a repair field region of a memory array, each having a fixed repair field size (RFS) of 1M (eight banks), respectively, of a prior art row redundancy system. In FIG. 1A, the row redundancy storage 10 is shown having storage cells 12 addressed as Bank0–127 storing redundancy information RI(1–16) corresponding, respectively, to 128 banks of the memory array.
In this case, 16 different sets of redundancy information RI(1–16) are stored, where each set of redundancy information corresponds to a repair field of 8 banks. As shown in FIG. 1A, one copy of each set of RI(n) is stored. Each set of RI(n) corresponds to one repair field, i.e., RI(1) corresponds to Banks0–7, RI(2) corresponds to Banks8–15, RI(16) corresponds to Banks120–127, etc.
Each set of redundancy information RI(n), includes 8 sets of 11 bits (or 88 bits). Each set of 11 bits represents a defective row address. Each defective row address indicates an address of a detected defective wordline. Eight redundant wordlines (RWL) are available for replacing defective wordlines detected in each repair field.
With reference to FIG. 1B, the repair field shown includes a set of eight banks, Bank0–7 forming a 1-megabyte (M) region. Each bank is traversed by 1,024 parallel wordlines WL(m), where m=0–1023, and 8 parallel redundant wordlines RWL(n), where n=0–7. Redundant wordlines RWL(0–7) are provided for replacing up to 8 possible failed wordlines of the wordlines WL(0–1023) within a bank. The redundant wordlines may be located anywhere within the bank however, typically, the row redundancy wordlines RWL(0–7) are located at the same location for each bank. In the example of FIG. 1B, the row redundancy wordlines RWL(0–7) are shown placed at the top portion of the bank.
A repair field size is defined as the minimal array size where repairing is done by the same set of given redundancy wordlines RWL(0–7). In FIG. 1B, the repair field size of row repair is 1M. When a wordline WL(m) is found to be defective within a bank, all the wordlines WL(m) across all eight banks (or the 1M region) within the repair field size are replaced by one redundancy wordline RWL(n), regardless of whether these wordlines WL(m) are defective or not. In the prior art example shown in FIG. 1B, only eight defective wordlines WL(m) with eight different row addresses are allowed in the whole 1M region. If more than eight wordlines WL(m) fail, the chip housing the 1M region is determined to be irreparable and must be discarded. In the prior art, the repairability of a memory chip is fixed, and once the RFS is defined in the design stage, it cannot be changed thereafter.
In the design stage, the repairability may be increased in order to improve yield. However, larger components are needed to accommodate increased repairability. For example, the size of an off-chip fuse bank used to store failed row information (row fuse information) discovered during a testing mode is proportional to the degree of repairability. Thus, the size of the fuse bank limits the degree of repairability of failed (faulty) wordlines WL(m).
Generally, the row redundancy is designed with the limited and inflexible repairability described above with reference to FIGS. 1A and 1B, which is sufficient once the technology has reached a mature stage, since the defect density becomes better controlled and the limited repairability is sufficient to get reasonable yield. Depending on the development stage of the memory design and/or related technology, different degrees of repairability may be desired. Greater repairability is typically desired at early stages of development, requiring a longer testing period and a larger storage area. Once the technology has reached a mature stage, it may be desirable to reduce the repairability in order to reduce the testing period and required storage area.
Accordingly, a need exists for a system and a method for selectably increasing repairability of a memory chip with a minimal increase in the size of circuitry associated with wordline repair. A need further exists for a system and method for flexible selection of repair field size.